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EMIF02-1003M6
2 line IPADTM, EMI filter and ESD protection in Micro QFN package
Features

Dual line EMI symmetrical (I/O) low-pass filter High efficiency in EMI filtering Very low PCB space consumption: 1.0 mm x 1.45 mm Very thin package: 0.6 mm max High efficiency in ESD suppression (IEC 61000-4-2 level 4). High reliability offered by monolithic integration High reduction of parasitic elements through integration and wafer level packaging. Lead free package Easy layout and flexibility due to single line topology Low capacitance
Micro QFN 1.45 mm x 1.00 mm (bottom view)
Figure 1.
Pin configuration (top view)
IN
1
6
OUT
Complies with following standards
IEC 61000-4-2 level 4, input and output pins - 15 kV (air discharge) - 8 kV (contact discharge) MIL STD 883G - Method 3015-7 Class 3B (all pins)
GND IN
2
5
GND OUT
3
4
Applications
Where EMI filtering in ESD sensitive equipment is required:

Figure 2.
Basic cell configuration
Keyboard for mobile phones Computers and printers Communication systems MCU Boards
Input R = 100 CLINE = 30 pF typ. @ 0 V
Output
Description
The EMIF02-1003M6 is a 2 line highly integrated device designed to suppress EMI/RFI noise in all systems exposed to electromagnetic interference. This filter includes ESD protection circuitry, which prevents damage to the application when subjected to ESD surges up to 15 kV on all pins.
TM: IPAD is a trademark of STMicroelectronics
October 2007
Rev 1
1/10
www.st.com
Characteristics
EMIF02-1003M6
1
Table 1.
Symbol VPP Tj Top Tstg
Characteristics
Absolute ratings (limiting values at Tamb = 25 C unless otherwise specified)
Parameter ESD discharge IEC61000-4-2 air discharge on input and output pins ESD discharge IEC61000-4-2 contact discharge on input and output pins Junction temperature Operating temperature range Storage temperature range Value 15 8 125 -40 to + 85 -55 to +150 Unit kV C C C
Table 2.
Symbol VBR IRM VRM VCL Rd IPP RI/O Cline Symbol VBR IRM RI/O Cline S21
Electrical characteristics (Tamb = 25 C)
Parameter
I
Breakdown voltage Leakage current @ VRM Stand-off voltage Clamping voltage Dynamic resistance Peak pulse current Series resistance between Input & Output Input capacitance per line Test conditions IR = 1 mA VRM = 3 V per line Tolerance 10% VR= 0 VDC, VOSC = 30 mV, F = 1 MHz F = 900 MHz 100 30 Min. 5 Typ. 6.5
VBR VCL VRM
IF
VF IRM IR V
IPP
Max. 8 100 39 -26
Unit V nA pF dB
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EMIF02-1003M6
Characteristics
Figure 3.
dB
S21(db) attenuation measurement (Vbias = 0 V)
Figure 4.
Analog cross talk measurements
dB
0.00
0.00
-15.00
-5.00
-30.00
-10.00
-45.00
-15.00
-60.00
-75.00
-20.00
-90.00
-25.00
-105.00
F (Hz)
-30.00 100.0k 1.0M I1-O1 10.0M 100.0M I2-O2 1.0G
-120.00 100.0k 1.0M I1-O2 10.0M
F (Hz)
100.0M I2-O1 1.0G
Figure 5.
ESD response to IEC 61000-4-2 Figure 6. (+15 kV air discharge) on one input and on one output
ESD response to IEC 61000-4-2 (- 15 kV air discharge) on one input and on one output
Input
Input
Output
Output
Figure 7.
Line capacitance versus reverse voltage applied (typical value)
35 30 25 20 15 10 5 0 0
C LINE (pF)
V LINE (V)
1 2 3 4 5
3/10
Application schematic
EMIF02-1003M6
2
Application schematic
Figure 8. Application schematic
1) Data lines protection
IN
1
6
OUT
Dat1
IC to Protect
GND 2 IN
3
5
GND OUT
4
Dat2
2) Keypad protection
IN
1
6
OUT
Keypad
GND 2
5
GND OUT
Controller
IN
3 4
Keypad
Keypad
3
Ordering information scheme
Figure 9. Ordering information scheme
EMIF EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10(pF) Package Mx = Micro QFN x leads
yy
-
xxx z
Mx
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EMIF02-1003M6
Package information
4
Package information
Epoxy meets UL94, V0
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Table 3. Micro QFN 1.45 x 1.00 6L dimensions
D
N
Dimensions Ref.
E
Millimeters Min. Typ. 0.55 0.02 0.25 1.45 1.00 0.50 0.20 0.30 0.35 0.40 0.008 Max. 0.60 0.05 0.30 Min.
Inches Typ. Max.
1
2
A A1
0.50 0.00 0.18
0.020 0.022 0.024 0.000 0.001 0.002 0.007 0.010 0.012 0.057 0.039 0.020
A A1
1 2
b D
L k b e
E e K L
0.012 0.014 0.016
Figure 10. Footprint in mm [inches]
0.50 [0.020] 0.25 [0.010]
Figure 11. Marking
Dot : Pi n 1 Identification XX = Marking
0.60 [0.023] 0.30 1.60 [0.012] [0.063]
F
5/10
Package information Figure 12. Tape and reel specification
Dot identifying pin 1 location
2.0+/-0.05 4.00+/-0.1 1.5 +/- 0.1
EMIF02-1003M6
1.75 +/- 0.1 3.5 +/- 0.03
0.75
8.0 +/- 0.3
1.65
F
F
F
1.20 User direction of unreeling
4.00
Note:
Product marking may be rotated by 90 for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose.
6/10
EMIF02-1003M6
Recommendation on PCB assembly
5
5.1
Recommendation on PCB assembly
Stencil opening design
1. General recommendation on stencil opening design a) Stencil Opening Dimensions: L (Length), W (Width), T (Thickness).
Figure 13. Stencil opening dimensions
L
T
W
b)
General Design Rule Stencil thickness (T) = 75 ~ 125 m W Aspect Ratio = ---- 1.5 T LxW Aspect Area = --------------------------- 0.66 2T ( L + W )
2.
Reference design a) b) c) Stencil opening thickness: 100 m Stencil opening for central exposed pad: Opening to footprint ratio is 50%. Stencil opening for leads: Opening to footprint ratio is 90%.
5.2
Solder paste
1. 2. 3. 4. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. "No clean" solder paste is recommended. Offers a high tack force to resist component movement during high speed Solder paste with fine particles: powder particle size is 20-45 m.
7/10
Recommendation on PCB assembly
EMIF02-1003M6
5.3
Placement
1. 2. 3. 4. Manual positioning is not recommended. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering Standard tolerance of 0.05 mm is recommended. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools.
5. 6.
5.4
PCB design preference
1. 2. To control the solder paste amount, the closed via is recommended instead of open vias. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away.
5.5
Reflow profile
Figure 14. ST ECOPACK recommended soldering reflow profile for PCB mounting
Temperature (C)
260C max 255C 220C 180C 125 C
2C/s recommended 2C/s recommended 6C/s max 6C/s max
3C/s max 3C/s max
0 0 1 2 3 4 5
10-30 sec 90 to 150 sec 90 sec max
6
7
Time (min)
Note:
Minimize air convection currents in the reflow oven to avoid component movement.
8/10
EMIF02-1003M6
Ordering information
6
Ordering information
Table 4. Ordering information
Marking F(1) Package Micro QFN Weight 2.2 mg Base qty 3000 Delivery mode Tape and reel (7")
Part number EMIF02-1003M6
1. The marking can be rotated by 90 to diferentiate assembly location
7
Revision history
Table 5.
Date 07-Oct-2007
Document revision history
Revision 1 Initial release. Changes
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EMIF02-1003M6
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